Serializer/De-serializer (SerDes) circuits are commonly used in high speed communications to increase the rate at which data can be sent and received. Serial communication is the process of sending data one bit at a time, sequentially, over a communication channel or computer bus. This is in contrast to parallel communication, where several bits are sent as a whole, on a link with several parallel channels. Serial communication is usually used for long-distance communication and by most computer networks where the cost of cables makes parallel communication impractical.
In general, data can be transmitted serially at faster rates than if transmitted in parallel because the electrical environment where data is sent can be better controlled. As a result, SerDes circuits usually convert data received in parallel to serial data before transmitting the data. After the data has been transmitted in series, the serial data is converted back to parallel data by SerDes circuits. Parallel data usually may be operated on (i.e. processed) at a higher rate than serial data.
The basic SerDes circuit is usually made up of two functional blocks: the Parallel In Serial Out (PISO) block (i.e. parallel-to-serial converter) and the Serial In Parallel Out (SIPO) block (i.e. serial-to-parallel converter). There are at least 4 different types of SerDes architectures: (1) Parallel clock SerDes, (2) Embedded clock SerDes, (3) 8b/10b SerDes, and (4) Bit interleaved SerDes.
The PISO block typically has a parallel clock input, a set of data input lines, and input data latches. The PISO block may use an internal or an external Phase-Locked Loop (PLL) to provide a clock signal to multiply the incoming parallel clock up to a higher serial frequency.
The SIPO block typically has a receive clock output, a set of data output lines and output data latches. The receive clock may be recovered from the data by a serial clock recovery technique. However, a SerDes circuit that does not transmit a clock uses reference clock to lock a PLL to the correct transmission frequency. The SIPO block then divides the incoming clock down to a parallel data rate.
The integrity of the clock signals used with SerDes circuits is important. Ideally, the variation in the period of a clock signal should be zero. However, in practice this is not the case. When the period of a clock signal varies, clock jitter is created. Clock jitter is a time variation in the period of the clock signal. Clock jitter degrades the transmission and reception of data in SerDes circuits. Therefore it is important to keep the variation in the period of a clock signal as low as possible in order to reduce clock jitter. Reducing clock jitter improves the quality of data transmission in SerDes circuits.